| 摘要 |
PURPOSE: To enable error detection and correction without being restricted by a data bus by integrating either of error detection and correction or both of them into the same integrated circuit chip as that of a data storage. CONSTITUTION: A storage device controller 22 is made to receive a control signal instructing to read or write data from or to a DRAM 28 and is made to output address and control signals to the storage device in response to the instruction. The data read or written are fed to an EEC circuit 36 at the same time, which checks PCRC bits 32 corresponding to the data read from the circuit 36 in response to a check/generation control signal 40, and generates bits corresponding to the written data. During a writing operation, it is judged whether or not an error is indicated by checking the bits 32 corresponding to the circuit 36, and if an error exists, it is corrected by the circuit 36 and is fed into a bus 34 to be stored in a DRAM 28, and is transmitted to a system bus 12 by a bus transceiver 26. During a writing operation, PCRC bits are generated corresponding to the data bits. |
