| 摘要 |
PURPOSE:To reduce the size of a serial transmission equipment and speed up its operation by allowing a transmitting and receiving circuit to share a shift register. CONSTITUTION:When a clock (a) is inputted to a shift register 3 of a master station 1, master station sent data (b) are sent to a serial transmission line 13 in order. When the frame head of slave station received data b' is inputted to a slave station 2, a slave station follow-up clock (d) is outputted from a clock generator 10 at the reception timing and slave station sent data (e) are outputted from a shift register 9 and sent to a serial transmission line 14. At the same time, the received data b' are inputted to the shift register 9, having sent the data, in order from the tail. The sent data (e) become master station received data e' through transmission delay and are inputted to the flip-flop 6 of the master station 1. A clock delay circuit 5 delays the clock (a) according to the transmission delay to place the flip-flop 6 in operation and the received data e' which are inputted in order are sent to the shift register 3. |
