发明名称 ERASING METHOD FOR SEMICONDUCTOR MEMORY
摘要 <p>PURPOSE:To suppress the variation of threshold value voltage between each bit caused by erasing in a stuck type flash EEPROM semiconductor memory, while to prevent the degradation of a cell current at the time of reading out. CONSTITUTION:At the time of erasing of a stuck type flash EE-PROM, high voltage is impressed to a source terminal or a gate terminal and low voltage is impressed to the source terminal, after all cell is excessively erased, voltage corresponding to a power supply voltage is impressed to a drain terminal or the source terminal. And after threshold level voltage of the cell is converged to a desired value, this time, by impressing the prescribed voltage to the gate terminal, threshold value voltage can be converged to a low value without degrading of a cell characteristic comparing with the case of a drain after excessive erasing or source stress.</p>
申请公布号 JPH0757485(A) 申请公布日期 1995.03.03
申请号 JP19930205012 申请日期 1993.08.19
申请人 MATSUSHITA ELECTRON CORP 发明人 FUKUMOTO KOTA
分类号 G11C17/00;G11C16/02;G11C16/04;G11C16/06;H01L21/8247;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):G11C16/06;H01L21/824 主分类号 G11C17/00
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