| 摘要 |
PURPOSE:To reduce power consumption by inhibiting the counting operation of a watchdog timer in a SLEEP mode and enabling the counting operation only when a CPU is in an operating state. CONSTITUTION:When the CPU 1 stops, i.e., a SLEEP signal S2 from a SLEEP flag 2 is '1', an AND gate 20 is closed and the input of a clock signal tphi to a free run counter 4 is inhibited to stop the counting signal phi to a free run counter 4 is inhibited to stop the counting operation of the counter 4. When a reset signal generating circuit 30 is accessed from the CPU 1 by a prescribed procedure, a reset signal generating circuit 30 generates a reset signal S3 to reset the counter 4, and also when the SLEEP signal S2 is switched from '1' to '0', i.e., when an interruption signal IR is inputted and the CPU 1 wakes up and starts operation, generates the reset signal S3 to reset the counter 4.
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