A detection unit (46) detects that an input pattern which is stored in an input-pattern memory (45) corresponds to a signal which is input into a logic circuit unit (2) having arbitrary structure. A prediction pattern which corresponds to the input pattern detected by the detection unit (46) is transferred from the prediction-pattern memory (52) to a comparator (6). The comparator (6) compares an output from the logic circuit unit (2) with the prediction pattern and then a fault-processing circuit (7) processes the comparison result. The fault-processing circuit (7) stores the details of the fault in a fault register (8) and makes the data in the register (8) transferrable via a data bus (34) out from a fault-detection circuit (101b). The information relating to the fault is processed with statistical evaluation and the data stored in the input-pattern memory (45) and the prediction-pattern memory (52) are correctly rewritten, so that the fault-detection rate can be improved. <IMAGE>
