| 摘要 |
<p>A microcomputer system providing high performance access to external Special Function Registers (SFRs) has an 8051 architecture microcontroller (302) modified such that the instruction stream can be externally examined and decoded by an external expansion decoder (304). Data on the internal bus of the modified microcontroller is transferred to the PORT2 pins and is available to the external expansion decoder (304). After reset, the EA pin (320) operates as a bidirectional control pin that, as an output, signals whether the current bus cycle is an instruction fetch, and, as an input, signals whether the microcontroller (302) shall read the data present on a certain set of I/O pins. The expansion decoder (304) determines whether the current instruction may operate on an SFR, decodes the SFR address of the current instruction, and produces appropriate control signals for accessing an external SFR. The system reduces external device access time by providing access to external devices as if they were architecturally internal devices.</p> |
