发明名称 ATA INTERFACE ARCHITECTURE EMPLOYING STATE MACHINES
摘要 An ATA interface apparatus (Fig. 5), within a storage system, for controlling the transfer of sectors of data between a host processor and a buffer (11) within the storage system in response to READ and WRITE command issued by the host processor, the apparatus (Fig. 5) comprising a Byte Count State Machine (4) for controlling the transfer of sectors of data between the host processor and the buffer (11), an Update Task File State Machine (5) having a machine cycle for decrementing by one the number of sectors still to be transferred after a sector has been transferred by the Byte Count State Machine (4), a Read State Machine (6) for controlling the processing of all READ commands issued by the host to the storage system and a Write State Machine (7) for controlling the processing of all WRITE commands issued by the host to the storage system.
申请公布号 WO9506284(A1) 申请公布日期 1995.03.02
申请号 WO1994US09386 申请日期 1994.08.22
申请人 CONNER PERIPHERALS, INC. 发明人 CLAY, DONALD, W.
分类号 G06F13/10;G06F3/06;(IPC1-7):G06F13/00 主分类号 G06F13/10
代理机构 代理人
主权项
地址