发明名称 IMAGE PROCESSOR
摘要 PURPOSE:To save memory capacity by reducing bit width from each original image by a non-linear conversion, etc., and storing plural images in a memory corresponding to one sheet of image by providing a means performing input/ output by a bit width which is smaller than the bit width of the input/output of a multilevel image memory of m-bit. CONSTITUTION:In an operation where two images are synthesized and are copied at a high speed, a first image is converted by a table conversion circuit 104 and a selector 105 selects the output. At this time, 8-bit digital data is compressed to 7-bit. The selector 105 is controlled to output the upper 7-bits of an 8-bit bus. A second image is also outputted to the 8-bit bus in the same way, and at this time, the image is compressed to 1-bit by a table conversion circuit 104. The selector 105 performs an output to the LSB of the 8-bit bus. Two images are stored in a memory 106 via the bus. At this time, a controller outputs an enable signal and reads and writes the upper 7-bit of the memory and the LSB independently.
申请公布号 JPH0757076(A) 申请公布日期 1995.03.03
申请号 JP19930223885 申请日期 1993.08.17
申请人 CANON INC 发明人 HORIUCHI IZURU
分类号 B41J5/30;G06T1/00;G06T1/60;G06T3/00;H04N1/387;(IPC1-7):G06T1/60 主分类号 B41J5/30
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