| 摘要 |
PURPOSE: To provide an analog multiplier with little power consumption, small area chip, improved linearity, and high processing speed, and extremely wider range of an input voltage than that of a conventional multiplier using only a bipolar transistor. CONSTITUTION: This device is provided with a buffering means connected through an output resistance (ROUT) with a positive power source (VDD) so that a multiplied output voltage (V<+> OUT, V<-> OUT) can be outputted, which inputs signal values (V<+> X, V<-> X) of a multiplier (multiplicand), first - fourth nMOSFET (M1-M4) whose drain terminals are connected with the buffering means, and to whose gate terminals multiplicand (multiplier) signal values (V<+> Y,V<-> Y) are inputted and which operates multiplication, and a bias current source (IB) connected with the first - fourth MOSFET (M1-M4), which supplies bias currents. |
