Memory addressing scheme for increasing the number of memory locations available in a computer for storing higher precision numbers.

摘要

A backward compatible addressing scheme for increasing the number of memory locations available in a computer for storing higher precision numbers. The computer system of the present invention has a processor capable of manipulating numbers having precision S, where S is a power of 2. The memory locations are specified in an instruction address field by an n-bit logical address $Each\; S-precision\; number\; is\; stored\; in\; a\; group\; of\; S\; memory\; locations\; accessed\; by\; an\; m-bit\; physical\; address$ Each\; memory\; location\; is\; capable\; of\; storing\; a\; single\; precision\; number.\; Addressing\; logic\; for\; addressing\; the\; memory\; locations\; with\; the\; logical\; addresses\; includes\; alignment\; logic\; for\; setting:\; di\; =\; 0\; for\; 00The\; extension\; logic\; may\; be\; implemented\; according\; to\; the\; logic\; equation$ n$$$