Reducing clock skew.

摘要

An integrated circuit comprises a plurality of internal data handling devices and a data buffer for transferring data between the internal data handling devices and one or more external data handling devices external to the integrated circuit. A control means, responsive to an original clock signal, supplies a clock signal to control data transfer between the data handling devices, the control means comprising a delay circuit to delay the original clock signal and selection means operable: (i) to select the original clock signal for controlling data transfer from an internal data handling device to another data handling device; and (ii) to select the delayed clock signal for controlling data transfer from an external data handling device to an internal data handling device.