发明名称 Return address appending mechanism intended to be used in a parallel processing system
摘要 When a memory access is to be effected in a parallel processing system, interfacing between the networks is simplified by generating a network control item in respect of the return of the data read from the networks and by embedding it within enquiries. For this purpose, toggles (14, 24, 34 and 44) identifying input port numbers are provided in each network across which enquiries are to be transferred, the identified input numbers are embedded in the enquiries so as to be transferred and, when the data return, this item is used as network switching control item. Furthermore, the arbitration outputs (71 to 74) contained in the networks across which enquiries are transferred are used as input port numbers. <IMAGE>
申请公布号 FR2709193(A1) 申请公布日期 1995.02.24
申请号 FR19940010115 申请日期 1994.08.18
申请人 NEC CORP 发明人 ODA MINORU
分类号 G06F13/16;G06F13/40;(IPC1-7):G06F13/38;G06F15/173 主分类号 G06F13/16
代理机构 代理人
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