发明名称 SEMICONDUCTOR MEMORY UNIT
摘要 <p>PURPOSE:To omit the diffusion region for earth line and thus to minimize the size of the cell by distributing plural units of IGFET at the matrix intersections and storing the binary information with setting of the conducting direction for the source PN junction with every IGFET. CONSTITUTION:Si gate type IGFET elements T11, T12, T21 and T22, address line A1 and A2 of the N<+>-type poly-crystal Si plus output line 01 and 02 composed of Al are formed respectively on the P-type Si substrate SUB. In this case, element T11 and T21 are located along line 01, and part of line A1 and A2 are positioned within opening part ACT1 for formation of the active region. At the same time, N<+>-type source region S1 and drain region DC of element T11 are provided across line A1, and N<+>-type source region S2 and drain region DC of element T21 are provided across line A2 respectively. In addition, P<+>-type region P1 is formed between region S1 and SUB and with an overlap to the PN junction, thus securing the reverse conduction for the junction.</p>
申请公布号 JPS54139492(A) 申请公布日期 1979.10.29
申请号 JP19780046526 申请日期 1978.04.21
申请人 HITACHI LTD 发明人 UCHIUMI CHIKATAKE
分类号 G11C17/00;H01L21/8246;H01L27/112 主分类号 G11C17/00
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