| 摘要 |
A cache controller apparatus for controlling an external write back cache memory and arbitrating a system bus, which interconnects a microprocessor having an internal write back cache memory, an external cache memory, a main memory, and one or more DMA controllers. The cache controller apparatus controls the write-back cycle of the external cache by imitating a microprocessor memory write cycle. The cache controller also insures the cache consistency of the cache internal to the microprocessor. When a DMA controller or ISA bus master is master of the system bus and asserts a valid memory command, the cache controller causes the DMA controller or ISA bus master to wait and the microprocessor to perform an internal cache inquiry to determine if the internal cache memory contains modified data to be stored at the memory location desired by the DMA controller. If the cache line needs to be written-back, the microprocessor signals the cache controller, which, in turn, provides the microprocessor with temporary mastership of the system bus, such that it can write back the cache line to the system. The cache controller invalidates a corresponding cache line in the external cache memory if it is valid. Finally, the external bus master is allowed to continue with the memory access. |
