| 摘要 |
<p>An ECC and/or ECC single burst trapping circuit is taught in which each such circuit has its state stored in the RAM and, in one embodiment, also allowing the use of a single general purpose multiplier rather than a large number of separate dedicated multipliers. Higher speed data rates available from current CMOS integrated circuit processes are utilized to share the higher speed operation of the single general purpose multiplier, while allowing the circuit to operate at sufficiently high speed to accommodate the speed of current and future disk drive technology. An M row x N column bit RAM is used to store the state of the circuit, decreasing the overall size of the integrated circuit. A single general purpose multiplier is used for the ECC generation detection circuit and a single set of an N bit wide exclusive OR gate arrays and multipliers is used for the ECC single burst trapper circuit. As the RAM is sequenced through its addresses, the single multiplier and exclusive OR gate array are used repeatedly to determine the result to be stored in the subsequent location of the RAM. A sequence made through M RAM locations, together with one additional step to load the hold register needed in the burst trapper architecture, completes the operation. In accordance with another embodiment, a plurality of parallel paths are used to speed operation of the device, each of the parallel paths having associated RAM and a general purpose multiplier.</p> |
