发明名称 |
Chip-auf-Chip-Verbindungsschema für integrierte Halbleiterschaltungen. |
摘要 |
Integrated circuit chip-to-chip interconnections are made via gold pads (24, 34) on each chip (101, 102) that are bonded to corresponding gold pads (14, 12) on a silicon wafer chip carrier (10). The pads on the chips and/or the pads on the carrier are characterized by texturing (roughening) with a feature size of the order of a micrometer or less, so that each of the pads on the chip can be attached to each of the pads on the carrier by compression bonding at room temperature-- i.e., cold-well bonding. In particular, the texturing of the gold pads on the silicon carrier is obtained by etching V-grooves locally on the surface of the underlying silicon carrier in the regions of the pads, thermally growing a silicon dioxide layer on the silicon carrier, and depositing the gold on the silicon dioxide layer. |
申请公布号 |
DE68918775(T2) |
申请公布日期 |
1995.02.16 |
申请号 |
DE1989618775T |
申请日期 |
1989.07.13 |
申请人 |
AT & T CORP., NEW YORK, N.Y., US |
发明人 |
BLONDER, GREG E., SUMMIT NEW JERSEY 07901, US;FULTON, THEODORE ALAN, WARREN NEW JERSEY 07060, US |
分类号 |
H01L21/60;H01L23/13;H01L23/14;H01L23/485 |
主分类号 |
H01L21/60 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|