PARALLEL TEST CIRCUIT OF SEMICONDUCTOR MEMORY CHIP

摘要

The test method for semiconductor memory cell employs a first comparing means controlled by a first control means; the second comparing means comparing the output of the first comparing means; the selecting means complementally activated to the second control means in order to control the output of the second comparing means; a control means controlling the output buffer hooked on both the output of the selecting means and the first control comparing means. The test method can be used for finding the malfunction cell during the wafer process or the packing process.