| 摘要 |
A row line (38a, 38b) associated with at least one row of memory cells in an integrated circuit memory array (10) having a plurality of row lines is driven by a drive/boot generator signal (RLXH) by first generating this drive signal using a drive signal generator (20) that is formed in a peripheral area (14) of the chip (10). The drive signal (RLXH) is transmitted to each of a plurality of predecoders (40) that are formed within the memory cell array area (12). At least one of the predecoders (40) is actuated to decode the drive signal (RLXH) onto a preselected one of a plurality of predecoder output lines (RDD0 - RDD3) in response to predetermined addressing signals (RF0-RF19). The drive signal (RLXH) is transmitted on the addressed predecoder output line (44) to each of a plurality of decoders (36) formed within the array area (12). At least one of the decoders (36) is actuated to decode the drive signal (RLXH) from the addressed predecoder output line (RDD0-RDD3) to at least an addressed one of a plurality of row lines (38a, 38b) in response to predetermined addressing signals (RF0-RF19). The preselected row lines (38a, 38b) are then driven and booted using the decoded drive/boot signal (RLXH). |
