| 摘要 |
<p>PURPOSE:To reduce the power consumption of a pipeline processing circuit. CONSTITUTION:Each stage is constituted of flip flops FF11,... (FF21...) and an integrated logical circuit C1(C2). Stall signals STL1, STL2,... for stopping a pipeline are delayed for one clock by flip flops FF10, FF20,.... A clock signal CLK is turned on/off by each stall signal STL1, STL2,... turned to clock signals CLK1, CLK2,..., and those clock signals are indivisually supplied to the flip flops of each stage. Thus, the clock supply/stop of each stage can be operated.</p> |
