| 摘要 |
A pipe-line processing system and its microprocessor using the system in which each command having a plurality of memory operands is divided into a plurality of inner commands, each having a single memory operand and wherein the inner commands are executed in parallel. Accordingly, calculation of at least one effective address of one memory operand and the processing of the other operand can be performed simultaneously, thereby realizing a high speed operation with a simple circuit construction.
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