| 摘要 |
A data processor wherein, in the case where an instruction decoder has decoded a multi-data transfer (storing or loading) instruction, bits in a register list outputted from the instruction decoder are searched by first and second priority encoders to encode respectively a position of "1" (or "0") and a position where "1" (or "0") is continued in two bits as binary digits, and when the encoded results do not coincide only one register corresponding to a bit position of the single "1" (or "0") is accessed, when the encoded results coincide the registers corresponding to the bit positions of the two continuous "1" (or "0") are accessed at the same time to process the multi-data transfer instruction effectively.
|
