| 摘要 |
PURPOSE:To prevent the generation of malfunction by reducing a capacity difference between digit lines. CONSTITUTION:Memory cells MC are connected to digit lines BLb1 to BLbn, BLt1 to BLtn and their gates are connected to word lines WL1H to WLnH, WL1L to WLnL. Precharging elements PTH, PTL are connected to the opposite side digit lines of sense amplifiers SA1H to SAnH, SA1L to SAnL and the digit lines BLb1 to BLbn, BLt1 to BLtn are short-circuited by a signal line PDL. Reference potential is injected into these digit lines by a signal from a reference level line VHL. Cell judging power is always injected into false digit lines DBLb1 to DBLbn, DBLt1 to DBLtn on a terminal plate 2 through the level line. In this constitution, accessory circuits especially including the sense amplifiers SA1H, SAnH are alternately arrayed at the interval of one or two rows and capacity unevenness between digit lines on both the ends of the plate 2 and thier adjcent digit lines are improved by uniformly inserting false digit lines connected to a false memory cell and a cell judging power supply, so that balance of digit lines can be secured and the malfunction in the reading/writing of information can be prevented from being occured. |
