| 摘要 |
PURPOSE:To improve the product yield of a dynamic RAM or the like provided with plural redundant word lines and redundant bit lines and especially adopting STC structure memory cells and to reduce its cost by reducing the abnormality generation rate of normal word and bit lines constituting a memory array and reducing also the abnormality generation rate of redundant word and bit lines to be used for defect saving. CONSTITUTION:Redundant word lines WRL0, WRL1, WRR0, WRR1 are arranged on positions most close to Y-system peripheral circuits such as sense amplifiers SA in respective memory arrays and redundant bit lines BRL0*, BRL1*, BRR0*, BRR1* are arranged on positions most close to X-system peripheral circuits such as X address decoders XDL, XDR. These reduntant word and bit lines are successively used for defect saving from the positions separated from the Y-system peripheral circuits or the X-system peripheral circuit, i.e., from the lines arranged on the inside of respective memory arrays. |
