| 摘要 |
An invention providing a hard limiter between the pulse width modulator and output drive transistors of a class-D amplifier is disclosed. The limiter functions by controlling the duty cycle of the pulse width modulator output, which directly corresponds to the magnitude of the voltage appearing across the load output transducer. The pulse width modulated (PWM) signal is compared to the outputs of a pair of one-shot circuits (single pulse generators). If either the positive pulse or the negative pulse of the PWM signal is shorter than the one-shot pulse, then the one-shot pulse is substituted for the PWM pulse. This sets the maximum and the minimum values for the duty cycle of the PWM signal, thereby limiting the positive and negative value of the corresponding output voltage.
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