| 摘要 |
<p>PURPOSE:To accelerate total instruction processing speed by successively analyzing/processing data for each bit or bit group in an instruction composed of (n) bits. CONSTITUTION:A CPU 2 with a clock CK at 4MHz, which is generated by a clock generator 3, as a basic clock is arranged inside a microcomputer 10. The instruction composed of (n) bits is serially transmitted from a commander 1 to the CPU 1. The instruction is meant for each bit or each bit group, received by the CPU 2 and successively analyzed/processed later according to the program of a ROM 4. The instruction processed by the CPU 2 controls a part 7 to be controlled at a robot 11 through an I/O interface 6. Since the instruction composed of (n) bits is successively analyzed/processed for each bit or each bit group, the instruction can be previously processed without waiting for the arrival of the final bit, and the total instruction processing speed can be accelerated.</p> |
