发明名称 Halbleiteranordnung, bei der in einem Chip ein N-Kanal-MOSFET, ein P-Kanal-MOSFET und eine nichtflüchtige Speicherzelle gebildet sind.
摘要 An n-channel MOSFET (102), a p-channel MOSFET (104) and a nonvolatile memory cell (100) are provided for the same semiconductor substrate (1). The nonvolatile memory cell (100) is formed on the semiconductor substrate (1), the n-channel MOSFET (102) is formed in a p-type well region (11) of the semiconductor substrate (1), and the p-channel MOSFET (104) is formed in an n-type well region (12) of the semiconductor substrate (1).
申请公布号 DE69015540(D1) 申请公布日期 1995.02.09
申请号 DE1990615540 申请日期 1990.10.05
申请人 KABUSHIKI KAISHA TOSHIBA, KAWASAKI, KANAGAWA, JP 发明人 UEMURA, TERUO, C/O INTELLECTUAL PROPERTY DIV., MINATO-KU, TOKYO 105, JP;HANADA, NAOKI, C/O INTELLECTUAL PROPERTY DIV., MINATO-KU, TOKYO 105, JP
分类号 H01L21/8238;H01L21/8247;H01L27/092;H01L27/105;H01L29/788;H01L29/792;(IPC1-7):H01L27/115 主分类号 H01L21/8238
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