| 摘要 |
PURPOSE:To generate the random number sequence which is the same as the random number sequence generated by a conventional random number generating method at high speed by using plural shift registers in parallel. CONSTITUTION:Each register rn-1, rn-3,...r3, r1, rn, rn-2...r4, r2 shifts imparted values to the right and outputs the values of the registers r1, r2 of the rightmost end of each shift register SR<1>, SR<2>. In the register rn-1 of the left end of the shift register SR<1>, the values where a linear conversion is performed for the value of each register r1, r2,...rn by a linear logical arithmetic circuit T<1> are inputted. In the register rn of the left end of the shift register SR<2>, the values where the linear conversion is performed for the value of each register r2, r3...rn and the output from other linear logical arithmetic circuit T<1> by a linear logical arithmetic circuit T<2> are inputted. Each processing is repeated. Therefore, random number generating all or part of two outputs or the composed value thereof, are obtained. This procedure is simultaneously performed for each shift register SR<1> and SR<2>. |
