| 摘要 |
PURPOSE:To provide an efficient test pattern preparation system for automatically generating a higher rank logic circuit composed of plural independent lower rank logic circuits and automatically preparing the test pattern of the higher rank logic circuit from the tent patterns for the respective lower rank logic circuits. CONSTITUTION:The connection information of the higher rank logic circuit is automatically generated through an input terminal connection means 110, a selector insertion means 120 and an output connection means 130 in a logic circuit connection part 100 to which the terminal information 50 of the respective lower rank logic circuits is inputted and the test pattern 70 of the higher rank logic circuit is automatically generated through an inter-hierarchy terminal tracing means 210, a hierarchy pattern editing means 220 and a pattern allocation means 230 in a hierarchy pattern preparation means 200 to which the connection information of the higher rank logic circuit and the test pattern information 60 of the respective lower rank logic circuits are inputted. |
