发明名称 VARIABLE-LENGTH SIGN DECODER
摘要 PURPOSE: To improve the operation speed of a variable length decoder by eliminating operation delay such as an element that constitutes the decoder. CONSTITUTION: A signal that controls a 1st latch 41, a 2nd latch 42 a barrel shifter 43, i.e., a carrier signal is directly supplied to the latches 41 and 42 without going through an AND gate 53, though which the barrel operation delay due to the two latches 41 and 42 no longer occurs. Also, the window length of a shifter 43 is made the same with the number of bits of a unit bit stream, also the position of the window is shiftable, and a stream from the shifter 43 is given to a look-up table memory 600. The memory 600 consists of a code word table 61, a code word run length table 62 and a code word table 63, given code word length is accumulated by an accumulator 51, an acquired code word length is latched by a 3rd latch and code word length that is accumulated in accordance with the lock signal is supplied to the shifter 43 as a barrel shifter control signal.
申请公布号 JPH0738445(A) 申请公布日期 1995.02.07
申请号 JP19940000054 申请日期 1994.01.04
申请人 DAIU DENSHI KK 发明人 BOKU RIYUUKEI
分类号 G06F5/00;G06T9/00;H03M7/40;H03M7/42;H04N7/26;(IPC1-7):H03M7/40;H04N7/24 主分类号 G06F5/00
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