| 摘要 |
PURPOSE:To improve the suppression quantity of re-quantization noise included in one bit signal by generating an RZ signal and its complementary inverse of RZ signal, delaying any of them by an integral multiple of one sampling period and generating an MPRZ signal to be added. CONSTITUTION:The S/N of an oversampling one-bit D/A converter employing sigma delta modulation is improved by increasing its sampling rate. An RZC signal is delayed by a T (one clock) to obtain an inverse of RZc and they are added analogically. The analog adder employs an inverting adder, but a noninverting adder may be used. The output waveform is entirely the same as that of a 2-stage shift adder signal of a PRZ signal. That is, the same frequency characteristic as the PRZ 2-stage shift addition is obtained by almost the same circuit scale as the PRZ system and a high performance one-bit D/A converter circuit is obtained by suppressing sufficiently an out-band undesired high frequency with a small circuit scale.
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