| 摘要 |
A variable drive output buffer circuit for use to drive memory address lines, or the like, in a computer system has the drive output connected in parallel to a group of output buffer drive circuits, each of which is supplied with the drive signal. Each of the output buffer drive circuits, preferably in the form of CMOS buffer circuits, is selectively individually enabled or disabled to select the optimum number of output drive circuits which are operated in parallel to supply the drive signal to the output bonding pad. All of the disabled drive circuits are placed in a high impedance state, so that they essentially are removed from the circuit and do not affect the total drive capability.
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