发明名称 DECODED COUNTER ENABLING ERROR CHECK AND SELF CORRECTION
摘要 PURPOSE: To precisely perform self-correcting by making one of shift registers that include (n) pieces of FFs have a synchronous set, making all the rest have a synchronous reset and also having a pull-up line. CONSTITUTION: Only a 1st FF of a chain has asynchronous set and all the rest FFs have asynchronous resetting means. More than two FFs include one, and when a 1st one among these ones reaches the last FF of the chain, synchronous set-reset operation is automatically triggered, all the ones but one finally exist in the 1st FF and then go through an set input of the 1st FF. When an FF does not include one, entire switches that are driven by each FF are opened, then, a pull-up line has a high level through the pull-up device. Thereby, the 1st FF of the chain loads one through the D input at effective front where signals continue, and the precise state of a CRS operation is established again.
申请公布号 JPH0738421(A) 申请公布日期 1995.02.07
申请号 JP19940162788 申请日期 1994.06.21
申请人 SGS THOMSON MICROELETTRONICA SPA 发明人 JIYONA FUCHIRI
分类号 H03K21/40;H03M13/00;(IPC1-7):H03K21/40 主分类号 H03K21/40
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