| 摘要 |
PURPOSE:To generate a sampling clock signal which is in optimum phase with simple constitution by detecting a sampling value of a sine wave at the time of the generation of plural phase clock signals and utilizing the maximum value of the difference. CONSTITUTION:A select timing signal for a phase clock signal P0 which is in phase with a reference clock signal is generated by a maximum value detector 236 and the signal P0 is supplied from a selecting circuit 231b to register RSs 233 and 234, an ALU 235, and a detector 236. The RS 233 holds the value of a clock line sine wave signal at the rise of the signal P0 and the RS 234 holds its held value. The ALU 235 calculates the differences between the current values and last values of the RSs 233 and 234 and the maximum difference is sent to the detector 236. Then different phase clock signals P1, P2, and P3 are selected in sequence and similarly processed. Consequently, the detector 236 generates a setting signal for the phase clock signal with which the maximum difference is obtained and the circuit 231b outputs the sampling clock signal corresponding to it. |
