| 摘要 |
<p>PURPOSE:To provide a clock switching circuit which switches a clock without generating a glitch noise as to the clock switching circuit which outputs by switching plural clocks with phases different from each other synchronized with a master clock arbitrarily. CONSTITUTION:A frequency divider circuit 1 generates a first clock CLK0 and a second CLK1 with different from each other by 90 deg. by frequency-dividing the master clock MCLK. A synchronizing circuit 2 is constituted of a first flip-flop 21 operated by the falling of the master clock MCLK, and a second flip-flop 22 operated by the rising of the master clock MCLK. A selection circuit 3 is constituted of AND circuits 31, 32 and an OR circuit 33. The synchronizing circuit 2 synchronizes an asynchronous selection signal with the master clock, and generates selection signals SEL0, SEL1 provided with front and rear edges at the phase in the neighborhood of the center of the prescribed logical values of the clocks CLK0, CLK1, respectively.</p> |
