发明名称 ERROR COUNT CIRCUIT
摘要 PURPOSE:To simplify the circuit and to suppress complicated configuration attended with the increase in digit number by forming an error count circuit measuring consecutively data of consecutive data strings for each block in the unit of m-sets and counting the number of error data for each block with one set of counters. CONSTITUTION:The circuit includes a block counter 1 counting the number (m) of data for one block, an error counter 2 counting the number of errors for one block, a selector 3 selecting an initial value at loading and an OR gate 4. When the block counter 1 finishes counting number of the (m), a carry is produced and an initial value is loaded to the block counter 1 and the error counter 2 for the measurement of a succeeding block by using the carry as the load signal. When no error is in existence, (n+1) is loaded to the error counter 2 at loading and the error count is started after loading. When any error is in existence at loading, a value (n) is loaded as if errors were counted at loading.
申请公布号 JPH0738422(A) 申请公布日期 1995.02.07
申请号 JP19930180558 申请日期 1993.07.22
申请人 NEC CORP;NEC ENG LTD 发明人 UENO TSUKASA;YAMAGUCHI SUSUMU
分类号 H03K21/40;(IPC1-7):H03K21/40 主分类号 H03K21/40
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