| 摘要 |
<p>A lock detect circuit (18) determines when a reference frequency and a feedback frequency are frequency locked using a reference counter (32) and a feedback counter (36). The reference counter (32) and the feedback counter (36) are clocked by the reference frequency and the feedback frequency, respectively. After a first period of time, the outputs of the counters are compared. The outputs of the counters are also compared at the end of a second period of time. To be frequency locked, the two count values must be equal at both the end of the first and the second periods of time. A count window is generated from the reference frequency signal to indicate a range of frequencies for which the feedback frequency is locked. Once lock is achieved, the count window is widened such that the feedback frequency is still within a lock range when some aliasing occurs. A phase-locked loop (PLL) (10) comprising a phase comparator (12) and a charge pump circuit (14) uses an output signal generated by the lock detect circuit to enhance the operation of the charge pump circuit so that the PLL (10) achieves lock more efficiently. <IMAGE></p> |
