发明名称 CONTROL SYSTEM OF BUFFER MEMORY
摘要 PURPOSE:To simplify the control of a memory method and to reduce its cost by providing an empty memory which is stored with information on an address, where a buffer memory writes data, by receiving a command from an address counter. CONSTITUTION:On a write cycle, a write cycle command is inputted to empty memory 5 and at the same time, a write cycle clock is supplied to buffer memory 1, memory 5 and address counter 2. As a result, FF6 is reset. Simultaneously, an address signal is sent from counter 2 to memories 1 and 5, input data are written to memory 1 in sequence, and memory 5 is stored with information on an address where a write to memory 1 ends. On a read cycle, next, a read cycle clock is sent to counter 2, which reads out data from memory 1 at every time of counting up. At the same time, the data are outputted to memory 5 as well and after the final data are read out, FF6 is reset by the output of memory 5, so that the command for the read cycle end will be sent out.
申请公布号 JPS54145444(A) 申请公布日期 1979.11.13
申请号 JP19780054324 申请日期 1978.05.08
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 DEMACHI KAZUNORI
分类号 G06F5/14;G06F5/10;G11C7/00;(IPC1-7):11C7/00 主分类号 G06F5/14
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