发明名称 DATA MEMORY CIRCUIT
摘要 PURPOSE:To maintain the same correct data extending over a long period of time, by rewriting the output of a majority-decision into the odd-numbered memories synchronizing with the dissidence signal of a dissidence detection circuit which receives the outputs of the memories. CONSTITUTION:When the odd-numbered rewritable memories 1-1 to 1-n maintain correct data in them while the same data are stored. Majority-decision circuit 2 outputs correct data and dissidence detection circuit 3 outputs no dissidence signal. Therefore, memory write circuit 4 never writes data into memories. When the data of half the memories and below in the memory group are supposed to be inverted due to an inefficient write, a dissidence signal is outputted from circuit 3. Circuit 2, on the other hand, generates the correct-data output continuously. Circuit 4, therefore, rewrites the correct data into the memory group synchronizing with the signal of circuit 3, so that outputs of memories 1-1 to 1-n will all be correct data.
申请公布号 JPS54145443(A) 申请公布日期 1979.11.13
申请号 JP19780053886 申请日期 1978.05.06
申请人 MITSUBISHI ELECTRIC CORP 发明人 MIYAZAKI MASAAKI
分类号 G11C7/00;G06F11/18 主分类号 G11C7/00
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