| 摘要 |
<p>An address decoder has a plurality of address comparator circuits (102,103,104) for respective address areas, each comparator circuit including a base address register (107;111;115), a mask register (105;109;113), an AND gate (106;110;114), and a comparator (108;112;116). An address data (101) outputted from a processor is inputted to the address comparator (102) where the AND circuit (106) takes an AND logic of each bit for the address (101) and an inverted value taken for each bit from the content of the mask register (105) and the result is compared to a starting address of the pertinent address area stored in the base address register (107). If the compared data are in accord, an address decoded signal (117) of "1" is outputted, which indicates that the address (101) is an address within the pertinent address area. The address comparators (103) and (104) function in the same way as the address comparator (102). A priority encoder (120) receives address decoded signals from the plurality of address comparator circuits and outputs a highest priority address decoded signal as a final output when it receives a plurality of in-accord address decoded signals. The address decoder is small in circuit scale and has address area expansion capability. <IMAGE></p> |
