发明名称 |
Threshold optimization for SOI transistors through use of negative charge in the gate oxide. |
摘要 |
<p>Threshold optimization for SOI transistors is achieved through the formation of a layer of charge (21) within the gate oxide (14), which layer has a polarity corresponding to that of the ion implantation (22) for threshold voltage control. A negative charge layer (21) is formed by furnishing trace amounts of aluminum on the substrate before growth of an oxide to form a portion of the gate oxide. The aluminum will form a charge layer (21) on the surface of the oxide (19) and an additional oxide (18) is then deposited on the same to form the gate oxide as a sandwich with the charge layer in the same. <IMAGE></p> |
申请公布号 |
EP0637061(A1) |
申请公布日期 |
1995.02.01 |
申请号 |
EP19940109842 |
申请日期 |
1994.06.24 |
申请人 |
DIGITAL EQUIPMENT CORPORATION |
发明人 |
DOYLE, BRIAN S.;PHILIPOSSIAN, ARA |
分类号 |
H01L21/28;H01L21/306;H01L21/316;H01L21/336;H01L29/49;H01L29/51;(IPC1-7):H01L21/28 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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