Circuit structure for a memory matrix and corresponding manufacturing method.

摘要

A circuit structure for a matrix of EEPROM memory cells, being of a type which comprises a matrix of cells (2) including plural rows (3) and columns (4), with each row (3) being provided with a word line (WL) and a control gate line (CG) and each column (4) having a bit line (BL); the bit lines (BL), moreover, are gathered into groups or bytes (9) of simultaneously addressable adjacent lines. Each cell (2) in the matrix incorporates a floating gate transistor (12) which is coupled to a control gate (8), connected to the control gate line (CG), and is connected serially to a selection transistor (5); also, the cells (2) of each individual byte (9) share their respective source areas (6), which areas are structurally independent for each byte (9) and are led to a corresponding source addressing line (SL) extending along a matrix column (7).