| 摘要 |
<p>PURPOSE:To realize the equi-load wiring in consideration of a cross capacity by roughly wiring the signal lines other than a clock signal line before wiring of the clock signal line and preferentially wiring the clock signal line thereafter. CONSTITUTION:In a step 202, cells other than clock logics are extracted from layout data 110 of cells and a logic file 108, and rough layout is performed with each cell as the object. Wiring passage number data 206 on the rough wiring lattice is obtained as the result of rough wiring, and the number of intersections in each wiring in the case of wiring of the clock signal line can be estimated by this data. In a step 203, wiring passage number data 202, clock logics, and layout information of cells to which the clock signal is inputted are inputted to perform the equi-load wiring of clock wirings for respective cells. With respect to calculation of the wiring load executed during the equi- load wiring, the capacity at the intersection in each clock wiring is obtained and is added to the capacity peculuar to the wiring.</p> |
