发明名称 Method for fabricating a semiconductor device having a capacitor with a conductive plug structure in a stacked memory cell
摘要 A method for fabricating a semiconductor device includes steps of: (a) forming a MIS type transistor having a gate electrode and a first source/drain region and a second source/drain on a semiconductor substrate, (b) forming a contact hole by causing an insulating layer and a pad material layer to grow over the semiconductor substrate. and removing selectively the insulating layer and the pad material layer to expose the first source/drain regions, (c) forming a conductive plug, which fills inside the contact hole, by forming a first conductive material layer and etching back this layer in such a way as to leave this layer only in the contact hole, and (d) forming a capacitor which has a first electrode being in contact with the conductive plug and extending in a cantilever-like form from the conductive plug, a dielectric film covering a surface of the first electrode, and a second electrode surrounding the first electrode through the dielectric film. In view of the presence of the conductive plug, the physical strength of the first electrode is enhanced and hence the production yield is enhanced.
申请公布号 US5385859(A) 申请公布日期 1995.01.31
申请号 US19930097395 申请日期 1993.07.23
申请人 NEC CORPORATION 发明人 ENOMOTO, SHUICHI
分类号 H01L21/318;H01L21/822;H01L21/8242;H01L27/04;H01L27/10;H01L27/108;(IPC1-7):H01L21/70;H01L27/00 主分类号 H01L21/318
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