| 摘要 |
A memory system (30), comprised of a plurality of banks (320-327) of DRAM devices (10) is controlled by a memory controller (34) that not only determines the presence and density of the DRAM devices upon power-up, but also controls their addressing during normal operation. The memory controller addresses the DRAM devices in each bank by providing each with a complete row address and a complete column address that simultaneously specifies the row and column address for the condition when the DRAM device is symmetric and asymmetric. In this way, the controller can accommodate both symmetric and asymmetric DRAM devices in the same bank.
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