| 摘要 |
<p>PURPOSE:To obtain a channel switch without an operation speed neck different from a common buffer switch, having a high memory utilizing efficiency than a cross point buffer switch and suitable for high speed large capacity tendency. CONSTITUTION:Switches 100, 200 and 300 are provided to input lines Ia, Ib, Ic respectively. Each of the switches 100, 200, 300 stores a cell inputted from one input line to a buffer memory at once and outputs the cell to any of output lines Oa, Ob, Oc depending on the destination. Each of the switches 100, 200, 300 is provided with a counter deciding an output timing to the output lines to avoid collision with a cell outputted from other switches.</p> |
