| 摘要 |
PURPOSE:To make it unnecessary to adjust the center frequency of a VCO by controlling the frequency of the VCO in the 1st high speed PLL circuit having high frequency by a control signal generated from a low speed PLL circuit. CONSTITUTION:Since a reference control signal generating circuit 4 forms a PLL feedback loop for reference frequency (fos) from a bias circuit 44 to an active filter 41, the phase of the filter 41 is stabilized by a phase difference 90 deg. from the output of a frequency conversion circuit 40 and the circuit 44 generates bias voltage corresponding to the phase difference and sends the bias voltage to respective active filters 41, 31. Thereby a center frequency setting circuit 3 also forms a PLL for the same frequency (fos) as the reference frequency (fos) by a route consisting of bias circuit 23, a VCO 20, a frequency conversion circuit 30, and the active filter 31 and a voltage value outputted from a loop filter 33 controls the low speed PLL circuit so as to maintain it at frequency (fo). |
