| 摘要 |
<p>PURPOSE:To form the frame synchronization circuit optimizing a synchronization time in a frame synchronization circuit for data or the like subjected to BCH coding and interleave-arrangement. CONSTITUTION:Data of interleaved frames in the unit of N bits from N sets of consecutive A-bit data and data resulting from the data delayed at a 1 interleave frame delay circuit 1 are inputted to a syndrome calculation section 2. Then the syndrome calculation section 2 obtains frame synchronization and gives a synchronizing signal and an out of synchronism signal to a backward protection circuit 3 and a forward protection circuit 4, an output of the backward protection circuit 3 is given to a set terminal of an FF 5 and an output of the forward protection circuit 4 is given to a reset terminal of the FF 5. Then an output of the FF 5 taking the synchronization is used to stop a pulse output of a reset pulse generating circuit 6 as a pulse whose width is one interleave frame at a period of (a value slightly larger than a backward protection stage number)X1 interleave frame width and an output of the FF 5 at the out of synchronism outputs a pulse from the reset pulse generating circuit 6.</p> |
