Redundancy decoder for an integrated semiconductor memory

摘要

A redundancy decoder is used to address memory cells used in a redundant mode in an integrated memory. Each decoder stage (1) has a switching transistor (T) and a connector (F) that can be broken together with a control circuit (2) that is located between the two. The control circuit can be used during the test phase to check the stage is programmed, i.e. to check if the connector (F) is intact. The control circuit has a flip flop controlling a transistor and can be set and reset to allow simulation of the action of the connector.