Architecture of realizing balance of bit line sense amplifier in DRAM cell array

摘要

The present invention provides an architecture of a DRAM cell array having a plurality of bit lines and word lines. The word lines are formed by arranging metal word lines on poly-silicon word lines in parallel, and two bit lines construct a column. The metal word lines and the poly-silicon word lines are contacted to each other every predetermined column. The contacts form metal shunted areas of word lines in a high bit density semiconductor device. In the present invention, the two bit lines that are located in the vicinity of metal shunted area are conjoined together in order to construct a column, and the column is connected to a bit line sense amplifier.