发明名称 Data transmission system.
摘要 The clock demodulator 25 continually demodulates the clock signal of the control CPU 7 transmitted from the clock modulator 10 of the center S. The terminal control CPU 23 performs processes such as transmission and reception of data with the demodulated clock signal as a reference clock. The time required to synchronize the clocks of the CPUs 7 and 23 is eliminated. Transmission and reception of data is executed quickly as soon as right of transmission is transferred to a terminal. <IMAGE>
申请公布号 EP0635982(A1) 申请公布日期 1995.01.25
申请号 EP19940305399 申请日期 1994.07.21
申请人 BROTHER KOGYO KABUSHIKI KAISHA;XING INC. 发明人 FUNAHASHI, YASUHIRO, C/O BROTHER KOGYO K. K.;IKAMI, KAZUNORI, C/O BROTHER KOGYO K. K.;NISHIMURA, OSAMU, C/O BROTHER KOGYO K. K.;KIYOHARA, YUJI, C/O. BROTHER KOGYO K.K.;HIBINO,YOSHIHIKO, C/O BROTHER KOGYO K.K.;YASUTOMO, YUICHI, C/O XING INC.
分类号 H04N7/14;H04J3/06;H04L12/40;H04N21/437;H04N21/647 主分类号 H04N7/14
代理机构 代理人
主权项
地址